Capturing The Value of Test
Production Platform for Device Quality and Cost of Manufacturing Reduction
Streetwise™, has been deployed in production, globally in a broad variety of semiconductor device manufacturing operations and fabless design centers since 2004, and has become the industry’s most advanced Statistical Post Processing analysis platform for maximizing device quality while at the same time providing proven multi-flow analysis methodologies for reducing device manufacturing costs.
Streetwise™, has been deployed in production, globally in a broad variety of semiconductor device manufacturing operations and fabless design centers since 2004, and has become the industry’s most advanced Statistical Post Processing analysis platform for maximizing device quality while at the same time providing proven multi-flow analysis methodologies for reducing device manufacturing costs.
Streetwise™ supports the use of basic Part Average Testing (PAT) guardbanding methods (see chart 1. below) recommended by the AEC in 1997. (http://www.aecouncil.com) While well understood, these guardbanding methods have recognized limitations and drawbacks.
Chart 1: AEC Q001 guideline for basic distribution N-Sigma outlier detections
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Moreover, Streetwise™ platform extends the ability to expose device marginalities well beyond these traditional PAT methodologies, and with more confidence, through the comprehensive application of Single Variant, Multivariate (NNR, Regression), Spatial, and Composite analysis methods applied in single or multiple data flow manufacturing environments.
Chart 2: Multivariate Hybrid Analysis (NNR)
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Chart 3: Multivariate Regression Analysis
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The increased analysis granularity Streetwise™ uniquely exposes dramatically extends the opportunity to employ advanced next generation feed forward adaptive test strategies as outlined in the latest International Technology Roadmap for Semiconductors (ITRS: http://www.itrs.net). The industry has recognized that the referenced Adaptive Test strategies are required as semiconductor device manufacturing cost and quality demands continue to drive the market forward.
Streetwise™ analysis uniquely identifies device performance variability which exposes performance marginalities on a per die basis for next process step or disposition decision. (see chart 4.)
Chart 4: Variance pareto across parametric tests on a per die basis
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Streetwise™ uniquely integrates comprehensive Geographical analysis with Parametric analysis given the combination of analysis types are considered fundamental in achieving a high efficiency and effectivity for device disposition decisions.
It has been widely documented within the industry that failed die and/or marginal performing die adjacencies must be considered in order to properly disposition target die.
The Streetwise™ analysis architecture leverages its innovative parametric analysis methods in order to expose geographic based marginalities that expose not only die related defects, but confirm process or systematic related defects within identified geographic regions of the wafer. Another fundamental comprehension of geographical analysis is achieved through stacked or composite level analysis.
The Streetwise™ analysis architecture leverages its innovative parametric analysis methods in order to expose geographic based marginalities that expose not only die related defects, but confirm process or systematic related defects within identified geographic regions of the wafer. Another fundamental comprehension of geographical analysis is achieved through stacked or composite level analysis.
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Chart 5: Regional geographic spatial analysis
Again, well documented within the industry, specific locations of the wafer may expose repeatable marginal die locations that may only be exposed through comprehensive Composite analysis methods.
Streetwise™ geographical analysis not only leverages Parametric analysis as described above, but also contains additional sophisticated analysis methods such as: failure and die marginality clustering, die location exclusion, proximity analysis, pattern detection, and sub-wafer regional statistical bin limit detections.
Streetwise™ analysis technologies have been field proven to apply these next generation process methodologies today by removing the barriers between wafer fab parametric data and wafer sort electrical test screenings and final outgoing inspection (see Freescale Press Release for more information).
Streetwise™ Engineering is a comprehensive product engineering workbench providing the user with an easy to use recipe development and validation environment. Recipe development and validation within the engineering workbench ensures absolute traceability and revision control when developed recipes are ultimately uploaded and released to the Streetwise™ Production Tool.
- Application operates on Engineer P.C. or Laptop
- Define Analysis and Binning Strategy
- Validate Analysis results using Data Results Viewer
- Linked to Production for Recipe Management (see recipe mgt chart)
- User Friendly GUI and Editor
- 2D & 3D Wafer view (see wafer view chart)
- Revision controlled recipe editor
- Data trends/histograms/paretos
- Wafer Statistics
Recipe Management
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2D & 3D Wafer View
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Streetwise™ Production is a robust production proven 24 X 7 platform that runs the workbench “recipe” ensuring worry free operation without the necessity of manual intervention by operators. Integration within manufacturing production operations is seamless and highly flexible by choosing either TCP/IP protocol socket connections, file based operations, or Web Services communications. Data analysis traceability is ensured while recipes and their corresponding analysis results are defined with four levels of granularity as Product Family, Recipe ID, Version and History.
- 24/7 hands free production operation
- Scalable software architecture
- Supports Clustered configuration for Automatic failover of application and database
- File, Socket, or Web Services Host Adapters
- Browser based In-Process status interrogation
- Lot results
- Wafer level results
- Automated email notification
- Processing error conditions
- Yield excursion notification
- Revision controlled traceability